1. Field of the Invention
The present invention relates to a lead-on-chip lead frame, and more particularly to a lead-on-chip lead frame used for highly integrated semiconductor memory devices in place of a multi-chip package. The present invention also relates to a semiconductor package using such a lead-on-chip lead frame.
2. Description of the Prior Art
Lead-on-chip lead frames have a structure in which leads are arranged on a chip, in order to fabricate highly integrated semiconductor memory devices having a reduced package area while involving a reduced generation of noise at power lines.
A brief description will be made in conjunction with such lead-on-chip lead frames used for highly integrated semiconductor memory devices.
Generally, a lead-on-chip lead frame has leads for power lines such as a ground voltage line and a supply voltage line, leads for control signals such as CASL (Low), CASU (Upper), WE (Write Enable), OE (Output Enable) and RAS signals, leads for input/output signals, and leads for address signals. Each lead has an end extending to a desired position on the central portion of a chip mounted on the frame. That is, the leads are wire-bonded at their ends to pads arranged on the central portion of the chip, respectively. Thus, an electric connection is obtained between the leads and chip. Since the pads are arranged on the central portion of the chip in such a structure, the length of signal transfer lines is minimized. It is also possible to achieve an easy design of signal transfer lines. Accordingly, a stable semiconductor device can be fabricated.
Another lead-on-chip lead frame structure has also been proposed. In this lead-on-chip lead frame structure, each signal transfer lead has an end extending to a desired position on the central portion of a chip mounted on the frame, as in the above-mentioned frame structure. The frame is also provided with power lines, such as a ground voltage lead and a supply voltage lead, extending longitudinally across the central portion of the chip. The power lines are electrically connected to pads on the chip by means of wire bonding.
In such a structure, the transfer of power is carried out by the ground voltage lead or supply voltage lead elongated to the central portion of the chip. Such a power line exhibits low resistance as compared to lines which are arranged as power lines on the chip. Accordingly, an advantage is that the operating speed is improved.
On the other hand, in the case of a highly integrated semiconductor device such as a DRAM of the 1 Giga grade, it may have a size which is too large for the device to be fabricated in a single stepper. In this case, the chip used for such a semiconductor device should be divided into two blocks for DRAM's of the 516 Mega grade. Each circuit block has independent pads for control signal lines, power lines, input/output signals and address signals so that the associated DRAM of, for example, the 512 Mega grade, can operate independently.
FIG. 1 illustrates a lead-on-chip lead frame having a conventional configuration and a chip mounted on the frame. As shown in FIG. 1, the chip, which is denoted by the reference numeral 10, is divided into two independent circuit blocks. The chip has left pads P1 . . . Pn arranged in a single line on the central portion of the left circuit block and right pads P'1 . . . P'n arranged in a single line on the central portion of the right circuit block. The left and right pads are connected to signal lines and power lines, and are independent from each other so as to operate respective DRAM's of, for example, the 512 Mega grade. Left leads L1 . . . Ln and right leads L'1 . . . L'n are also arranged on the chip 10 in such a manner that they have ends respectively disposed adjacent to the left and right pads. The left leads L1 . . . Ln and right leads L'1 . . . L'n extend laterally from the associated pads in such a manner that they protrude from the associated sides of the chip 10, respectively.
On the other hand, FIG. 2 illustrates a lead-on-chip lead frame having another conventional configuration and a chip mounted on the frame. As shown in FIG. 2, the chip, which is denoted by the reference numeral 10, has left pads P1 . . . Pn arranged in a single line on the central portion of the chip 10 and right pads P'1 . . . P'n arranged in a single line on the central portion of the chip 10. Left leads L1 . . . Ln and right leads L'1 . . . L'n are also arranged on the chip 10 in such a manner that they have ends respectively disposed adjacent to the left and right pads. The leads L1 and Ln are connected to each other by a line 20 which is connected to both the leads L1 and Ln while extending along the empty space of the central portion of the chip 10. The leads L'1 and L'n are connected to each other by a line 30 which is connected to both the leads L'1 and L'n while extending along the empty space of the central portion of the chip 10.
FIG. 3 illustrates a semiconductor package which is fabricated by mounting a chip on a lead-on-chip lead frame having the configuration of FIG. 1 or FIG. 2 and performing a wire bonding process and a molding process for the chip-mounted lead frame. As shown in FIG. 3, the semiconductor package has 86 leads which are indexed with their functions or purposes at their ends, respectively. That is, the semiconductor package is provided with leads 1, 18, 69 and 86 for supply voltage VCC, leads 2, 6, 14, 73, 77 and 85 for supply voltage VCCq, leads 19, 42, 45 and 68 for ground voltage VSS, leads 3, 7, 15, 76, 81 and 84 for ground voltage VSSq, leads 23, 24, 25, 26, 61, 62, 64 and 69 for control signals such as CASL, CASU, WE, OE and RAS signals, leads 4, 5, . . . 16 and 17 for input/output signals I/O0 to I/O7, leads 70, 71 . . . 82 and 83 for input/output signals I/O8 to I/O15, and leads 27 . . . 41 and 46 . . . 60 for address signals A0 to A14. Since this configuration has a laterally-symmetrical pad/lead arrangement, it requires a large number of leads.